The packaging of electronic devices is becoming more important as demands increase for miniaturization, speed, improved reliability, weight reduction and security. A variety packages are under development such as a die-scale package, at a wafer level; and a die stack-type package. Die have been attached to an interposer to mount the die onto a printed circuit board (PCB) through an organic package substrate to translate the fine geometries of the interposer to the much larger spacing of the printed circuit board. An increasing number of conductive pads of the printed circuit board must be coordinated with more bonding pads on the semiconductor die to improve input/output (I/O) throughput.
As Moore's law approaches its decrescendo and the cost per transistor increases below the 22 nm node, device makers are seeking alternative solutions to stay competitive. 2.5D/3D heterogeneous integration has become an alternative solution to achieve higher yield, shorter interconnect length, shorter delays, reduced power, smaller footprint, reduced weight and higher performance. In homogeneous 2.5D/3D integration approach, as illustrated in FIG. 1A, a single chip 100 is partitioned into number of smaller chips (105, 110, 115, 120). Smaller chips (105, 110, 115, 120) are then assembled onto interposer 125 and wired together to form an integrated circuit. FIG. 1B shows a heterogeneous 2.5D/3D integration approach, a single chip 130 includes a number of circuitry blocks including memory 135, logic 140, DSP 145, and RF 150 manufactured separately and mounted on interposer 155 and wired together to form an integrated circuit. Smaller chips (135, 140, 145, 150) may be manufactured by different foundries and may have different process nodes selected for performance, availability and/or cost reasons.
The semiconductor industry has been transitioning from the traditional 2D monolithic approach to the 2.5D/3D heterogeneous approach at a much slower rate than expected. The slow acceptance has arisen due to the high cost. The high cost has resulted from difficult manufacturing procedures, poor reliability and low yield.
Devices are needed which lower the cost per transistor and integrated circuit in multi-level packages.